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/hsb-ip-create-top

@283faf4
by NVIDIA Corporationnvidia/skills3.5k stars
424

Create or explain fixed-format HSB FPGA_top.sv wrappers from validated HOLOLINK_def.svh files. Do not use for def generation or validation.

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Use this Skill: https://skilld.dev/gh/nvidia/skills/hsb-ip-create-top

This session only. Nothing lands on disk.

referenceshandoff-contract.md

≈417 tokens on demand. Your agent reads this file only when SKILL.md points to it.

Handoff Contract

Use this reference when coordinating hsb-ip-create-top with hsb-ip-def.

Standalone Prerequisite

When invoked directly, this skill requires a validated HOLOLINK_def.svh.

If the user has no defs file:

  1. Stop top-generation work.
  2. Tell the user to use hsb-ip-def to generate and validate HOLOLINK_def.svh.
  3. Resume only after a valid defs file path or content is available.

If the user has a defs file but validation status is unknown, ask to validate it with hsb-ip-def before proceeding.

Def-Skill Handoff

After hsb-ip-def successfully generates and validates a HOLOLINK_def.svh, it may ask:

Do you want to create a matching top-level FPGA scaffold with hsb-ip-create-top?

When the user says yes, the def skill should pass or summarize:

  • validated defs file path or content
  • known generated profile values, if available
  • selected HSB IP source root, if known
  • intended output path, if the user already supplied one

hsb-ip-create-top consumes that context and should not re-ask completed defs decisions.

Output Contract

The create-top skill outputs either:

  • a written FPGA_top.sv file, when the user asks for a file path, or
  • a fenced systemverilog scaffold, when the user asks for text.

After output, summarize:

  • active signal groups emitted,
  • groups omitted because the defs macro is undefined,
  • whether live HOLOLINK_top.sv or bundled known-rev references supplied the port map,
  • the generic note: "This file is a reference/template for hooking up top-level signals and companion IP to the HSB IP."

Do not enumerate what is outside the scaffold's scope in the summary.

Source: SKILL.md on GitHub

Third-party checks

1 warning1mo3 checks · Risk SAFE
  • Gen Agent Trust Hub1mo

    The skill is a specialized SystemVerilog scaffold generator for NVIDIA HSB IP integration. It operates locally on project source files to extract hardware interface definitions and produce templated wrappers. No malicious patterns, network exfiltration, or unauthorized code execution were detected.

  • Socket1mo

    No alerts

  • Snyk1mo

    Risk: MEDIUM · 1 issue

Provenance

Signed by skilld at 283faf4. This ties the file your Agent reads to that commit on GitHub. It does not review the instructions.

Last checked against GitHub yesterday.

Activeupdated 2 months ago

Capability

author
Holoscan Team <holoscan-team@nvidia.com>
version
0.1.0
tags
[
  "holoscan",
  "hsb",
  "fpga",
  "systemverilog",
  "top-level"
]
Other metadata
compatibility
Targets HSB IP rev 16'h2604; backward-compatible with 16'h2603. Prefer live HSB IP source when available; warn on unknown revisions. Designed to work standalone or as a companion to hsb-ip-def.
metadata
{
  "author": "Holoscan Team <holoscan-team@nvidia.com>",
  "team": "holoscan",
  "domain": "fpga",
  "vendor": "nvidia",
  "tags": [
    "holoscan",
    "hsb",
    "fpga",
    "top-level",
    "systemverilog"
  ],
  "languages": [
    "systemverilog"
  ],
  "artifact": "FPGA_top.sv",
  "source_artifact": "HOLOLINK_def.svh",
  "hsb_ip_version": "16'h2604"
}

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