skilld
All skills
nvidia avatar

/hsb-ip-create-top

@283faf4
by NVIDIA Corporationnvidia/skills3.5k stars
424

Create or explain fixed-format HSB FPGA_top.sv wrappers from validated HOLOLINK_def.svh files. Do not use for def generation or validation.

Ask your Agent

Use this Skill: https://skilld.dev/gh/nvidia/skills/hsb-ip-create-top

This session only. Nothing lands on disk.

referencessource-policy.md

≈633 tokens on demand. Your agent reads this file only when SKILL.md points to it.

Source And Version Policy

Use this reference when locating the HSB IP source or handling IP revision changes.

Source Authority

Live HSB IP source is authoritative when available. Bundled skill references describe known rev 16'h2604 and backward-compatible rev 16'h2603; a checked-out HOLOLINK_top.sv wins for the user's design.

Known source roots:

Layout Root path
NVIDIA-internal workspace hw/nvcpu_dgx_fpga/vrtl/hololink/
NVIDIA-internal sibling checkout hsb_agent/hw/nvcpu_dgx_fpga/vrtl/hololink/
Public release fpga/nv_hsb_ip/

These are search hints for the agent. Do not present them as radio-button choices to the user.

The top-level module source is:

<hsb-ip-root>/top/HOLOLINK_top.sv

Version Check

Read these localparams from HOLOLINK_top.sv when source is present:

localparam HOLOLINK_REV = 16'h2604;
localparam HOLOLINK_BACKWARD_COMPAT_REV = 16'h2603;

If the revision is 16'h2604 or backward-compatible with 16'h2603, proceed normally. If it is newer, unknown, or locally modified, parse the live module declaration and warn that bundled references may need an update.

If the user's current working directory is not the HSB source checkout, search obvious sibling paths before falling back to bundled references. If the source is still unclear, ask one plain-language question:

Do you have a current HSB IP `HOLOLINK_top.sv` source checkout you want me to use for port extraction, or should I use the skill's bundled known-rev port reference?

Accept either a path or a "use bundled reference" answer.

Port Source Of Truth

For FPGA_top.sv generation, derive the HSB-facing signal groups from the live HOLOLINK_top module declaration:

  • port name
  • direction
  • packed/unpacked width
  • ordering
  • comment group
  • ifdef / ifndef gate

Do not rely on example top-level files as IO authority.

Historical Example Top Files

The fixed output format is baked into references/fixed-format.md. Do not read example top files during normal generation just to confirm formatting.

Only inspect historical example top files when the user explicitly asks to compare, explain, or adapt a specific existing project:

  • hw/nvcpu_dgx_fpga/vrtl/bajoran_lite/top/FPGA_top.sv
  • hw/nvcpu_dgx_fpga/vrtl/bajoran/top/FPGA_top.v
  • hw/nvcpu_dgx_fpga/vrtl/bajoran_rfsoc/top/FPGA_top.sv

Do not copy project-specific implementation logic unless the user explicitly requests a project-specific adaptation.

Source: SKILL.md on GitHub

Third-party checks

1 warning1mo3 checks · Risk SAFE
  • Gen Agent Trust Hub1mo

    The skill is a specialized SystemVerilog scaffold generator for NVIDIA HSB IP integration. It operates locally on project source files to extract hardware interface definitions and produce templated wrappers. No malicious patterns, network exfiltration, or unauthorized code execution were detected.

  • Socket1mo

    No alerts

  • Snyk1mo

    Risk: MEDIUM · 1 issue

Provenance

Signed by skilld at 283faf4. This ties the file your Agent reads to that commit on GitHub. It does not review the instructions.

Last checked against GitHub yesterday.

Activeupdated 2 months ago

Capability

author
Holoscan Team <holoscan-team@nvidia.com>
version
0.1.0
tags
[
  "holoscan",
  "hsb",
  "fpga",
  "systemverilog",
  "top-level"
]
Other metadata
compatibility
Targets HSB IP rev 16'h2604; backward-compatible with 16'h2603. Prefer live HSB IP source when available; warn on unknown revisions. Designed to work standalone or as a companion to hsb-ip-def.
metadata
{
  "author": "Holoscan Team <holoscan-team@nvidia.com>",
  "team": "holoscan",
  "domain": "fpga",
  "vendor": "nvidia",
  "tags": [
    "holoscan",
    "hsb",
    "fpga",
    "top-level",
    "systemverilog"
  ],
  "languages": [
    "systemverilog"
  ],
  "artifact": "FPGA_top.sv",
  "source_artifact": "HOLOLINK_def.svh",
  "hsb_ip_version": "16'h2604"
}

README badge

README badge for nvidia/skills/hsb-ip-create-top